source [find mfg-jtag.cfg]

# Slow speed to be sure it will work
adapter_khz 3000

reset_config srst_only

# the only possible transport is JTAG
transport select jtag

jtag_nsrst_delay 500

source [find ../imx6ull.cfg]

# function to apply initial configuration after a reset. It
# provides a basic pad configuration and also DDR memory and clocks
# sufficient to load and execute a boot loader (e.g. barebox) from
# DDR memory. This list is extracted from the barebox flash image
# header.
proc apply_dcd { } {
	# Based on the I.MX6ULL_DDR3_Script_Aid_V0.01.xls init script
	# for i.MX6ULL DDR3 from https://community.nxp.com/docs/DOC-333791

	# Enable all clocks (they are disabled by ROM code)
	mww 0x020c4068 0xffffffff
	mww 0x020c406c 0xffffffff
	mww 0x020c4070 0xffffffff
	mww 0x020c4074 0xffffffff
	mww 0x020c4078 0xffffffff
	mww 0x020c407c 0xffffffff
	mww 0x020c4080 0xffffffff

	#
	# IOMUX
	#

	#DDR IO TYPE:
	# IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
	mww 0x020e04b4 0x000C0000
	# IOMUXC_SW_PAD_CTL_GRP_DDRPKE
	mww 0x020e04ac 0x00000000

	#CLOCK:
	# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
	mww 0x020e027c 0x00000030

	#ADDRESS:
	# IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
	mww 0x020e0250 0x00000030
	# IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
	mww 0x020e024c 0x00000030
	# IOMUXC_SW_PAD_CTL_GRP_ADDDS
	mww 0x020e0490 0x00000030

	#Control:
	# IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
	mww 0x020e0288 0x000C0030
	# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
	mww 0x020e0270 0x00000000
	# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
	mww 0x020e0260 0x00000030
	# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
	mww 0x020e0264 0x00000030
	# IOMUXC_SW_PAD_CTL_GRP_CTLDS
	mww 0x020e04A0 0x00000030

	#Data Strobes:
	# IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
	mww 0x020e0494 0x00020000
	# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
	mww 0x020e0280 0x00000030
	# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
	mww 0x020e0284 0x00000030

	#Data:
	# IOMUXC_SW_PAD_CTL_GRP_DDRMODE
	mww 0x020e04B0 0x00020000
	# IOMUXC_SW_PAD_CTL_GRP_B0DS
	mww 0x020e0498 0x00000030
	# IOMUXC_SW_PAD_CTL_GRP_B1DS
	mww 0x020e04A4 0x00000030

	# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
	mww 0x020e0244 0x00000030
	# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
	mww 0x020e0248 0x00000030

	#
	# DDR Controller Registers
	#
	# Manufacturer:	Micron
	# Device Part Number:	MT41K128M16JT-107:K
	# Clock Freq.:		400MHz
	# Density per CS in Gb: 2
	# Chip Selects used:	1
	# Number of Banks:	8
	# Row address:		14
	# Column address:	10
	# Data bus width	16
	#

	# MMDC0_MDSCR, set the Configuration request bit during MMDC set up
	mww 0x021b001c 0x00008000

	#
	# Calibration setup.
	#

	# DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
	mww 0x021b0800 0xa1390003

	# For target board, may need to run write leveling calibration to fine tune these settings.
	mww 0x021b080c 0x00000004

	#Read DQS Gating calibration
	# MPDGCTRL0 PHY0 - the xls file proposed 0x00000000
	mww 0x021b083c 0x41640158

	#Read calibration
	# MPRDDLCTL PHY0 - the xls file proposed 0x40404040
	mww 0x021b0848 0x40403237

	#Write calibration
	# MPWRDLCTL PHY0 - the xls file proposed 0x40404040
	mww 0x021b0850 0x40403C33

	#read data bit delay: (3 is the reccommended default value, although out of reset value is 0)
	# MMDC_MPRDDQBY0DL
	mww 0x021b081c 0x33333333
	# MMDC_MPRDDQBY1DL
	mww 0x021b0820 0x33333333

	#write data bit delay:
	# MMDC_MPWRDQBY0DL
	mww 0x021b082c 0xf3333333
	# MMDC_MPWRDQBY1DL
	mww 0x021b0830 0xf3333333

	#DQS&CLK Duty Cycle
	# [MMDC_MPDCCR] MMDC Duty Cycle Control Register
	mww 0x021b08c0 0x00944009

	# Complete calibration by forced measurement:
	# DDR_PHY_P0_MPMUR0, frc_msr
	mww 0x021b08b8 0x00000800

	#
	# Calibration setup end
	#

	#MMDC init:
	# MMDC0_MDPDC
	mww 0x021b0004 0x0002002D
	# MMDC0_MDOTC - the xls file proposed 0x1B333030, but maximum values of tAONPD/tAOFFPD is (2-8ns/2.5ns)=3CK instead of 4CK
	mww 0x021b0008 0x09333030
	# MMDC0_MDCFG0
	mww 0x021b000C 0x676B52F3
	# MMDC0_MDCFG1
	mww 0x021b0010 0xB66D0B63
	# MMDC0_MDCFG2
	mww 0x021b0014 0x01FF00DB

	# MMDC0_MDMISC
	# - CK1_GATING = 1 (MMDC drives only one clock toward the DDR memory (CK0));
	# - WALAT = 0 (No additional latency required);
	# - LPDDR2_S2 = 0 (This bit should be cleared in DDR3 mode);
	# - MIF3_MODE = 3 (Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus, Next miss access from access queue);
	# - RALAT = 5 (5 cycles additional latency).
	mww 0x021b0018 0x00201740
	# MMDC0_MDSCR, set the Configuration request bit during MMDC set up
	mww 0x021b001c 0x00008000
	# MMDC0_MDRWD
	mww 0x021b002c 0x000026D2
	# MMDC0_MDOR
	mww 0x021b0030 0x006B1023
	# Chan0 CS0_END
	mww 0x021b0040 0x0000004F
	# MMDC0_MDCTL
	mww 0x021b0000 0x83180000

	# MPPDCMPR2
	mww 0x021b0890 0x00400000

	#Mode register writes
	# MMDC0_MDSCR, MR2 write, CS0
	# - 60Ohm ODT;
	# - CWL = 5CK.
	mww 0x021b001c 0x02008032
	# MMDC0_MDSCR, MR3 write, CS0
	mww 0x021b001c 0x00008033
	# MMDC0_MDSCR, MR1 write, CS0
	# - Qoff disabled;
	# - TDQS disabled;
	# - 60Ohm ODT;
	# - Write leveling disabled;
	# - AL = 0;
	# - Out drive strength 40Ohm;
	# - DLL enable (normal).
	mww 0x021b001c 0x00048031
	# MMDC0_MDSCR, MR0write, CS0
	# - DLLon - fast precharge PD;
	# - Write recovery = 6;
	# - DLL reset = yes;
	# - CL = 6CK;
	# - Read burst type = sequential;
	# - Burst length = 8.
	mww 0x021b001c 0x15208030
	# MMDC0_MDSCR, ZQ calibration command sent to device on CS0
	mww 0x021b001c 0x04008040

	# MMDC0_MDREF
	mww 0x021b0020 0x00000800

	# DDR_PHY_P0_MPODTCTRL
	mww 0x021b0818 0x00000227
	# MMDC0_MDPDC now SDCTL power down enabled
	mww 0x021b0004 0x0002552D
	# MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
	mww 0x021b0404 0x00011006
	# MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
	mww 0x021b001c 0x00000000
}

# disable watchdog
proc disable_wdog { } {
	mwh 0x020bc000 0x30
}

# This function applies the initial configuration after a "reset init"
# command
proc som_init { } {
	global _TARGETNAME
	$_TARGETNAME arm core_state arm
	disable_wdog
	apply_dcd
}

# prevent cortex-a code from asserting SRST again
$_TARGETNAME configure -event reset-assert { }
# hook the init function into the reset-init event
$_TARGETNAME configure -event reset-init { som_init }
# make sure target is halted when gdb attaches
$_TARGETNAME configure -event gdb-attach { halt }