Emcraft Systems' system-on-module (SOM) runs the SmartFusion2 reference clock at 166MHz. PCLK is configured to run at a half of that rate, i.e. PLCK = 83MHz. The SPI controller allows bus rates of PLCK / 2 (or less), which, in the given configuration, translates to 41.5 MHz max for the SPI bus frequency.

To achieve optimal performance, both the U-Boot and Linux SPI device drivers make use of the on-chip DMA to transfer data between memory buffers and the bus.

Disregarding the overhead of SPI set-up commands, etc, a rough estimate of the theoretically possible data throughput when running SPI full-throttle at 41MHz is ~5.18MB/sec. In practice, we are able to load a 15MB file from SPI Flash to DDR in U-Boot in precisely 5 seconds (i.e. at a 3MB/sec rate). This number scales down proportionally as we decrease the SPI bus frequency (at 40MHz the same file is loaded in 3.15 sec; at 10MHz - in 12.6 sec), indicating that data is transferred back-to-back on the SPI bus. We are able to confirm back-to-back transfers using hardware analyzers attached to the SPI bus.

In uClinux, the raw SPI Flash throughput is measured to be the following, for read and write accesses respectively:

spi_m2s spi_m2s.0: SPI Controller 0 at 40001000,clk=83000000
...
~ # dd if=/dev/mtd2 of=/tmp bs=4M count=1

1+0 records in
1+0 records out
4194304 bytes (4.0MB) copied, 1.017328 seconds, 3.9MB/s
~ # dd if=/tmp of=/dev/mtd2 bs=4M count=1
1+0 records in
1+0 records out
4194304 bytes (4.0MB) copied, 10.763225 seconds, 380.6KB/s
~ #

Note that unlike U-Boot, which runs code from eNVM and keeps data in eSRAM, uClinux runs from DDR, which, although cached for code, is slower compared to the on-chip memory. Another consideration is that in uClinux there is some overhead for running the task scheduler and other processes executing in parallel with dd.