Developing M4 Firmware Print

 

This application note provides some initial pointers in regards to development of firmware for the M4 core of the STM32MP1 processor device.

ST provides many example projects for the M4 core contained in the STM32CubeMP1 firmware package:

https://www.st.com/content/st_com/en/products/embedded-software/mcu-mpu-embedded-software/stm32-embedded-software/stm32cube-mcu-mpu-packages/stm32cubemp1.html

This package can be installed via STM32CubeMx just like all the other ST firmware packages or downloaded directly at the link above. Once you download this package and unzip it, navigate to the ...\STM32Cube_FW_MP1_V1.0.0\Project\STM32CubeProjectsList.html file. This file contains a list of tools and projects, including information of which core(s) can be targeted.

The package contains examples for how to use various I/O interfaces on the M4 core: SPI, I2C, GPIO and others. Corresponding code can be used as a starting point in custom application development. In a typical STM32MP1 application, M4 firmware will communicate to Linux running on the Cortex-A core via the RPMSG messaging framework. Refer to Loading Firmware to the M4 Core and Using RPMSG for Inter-core Communications for a reference to an M4 application that provides sample code illustrating use of RPMSG messaging. The code in that application can be combined with the code in I/O-centered M4 examples, so as to develop an M4 application that both controls various I/O interaces and talks to Linux on the Corter-A cores via the RPMSG interface.

Note that for any I/O interfaces allocated to the M4 core, there might be a need to update the Linux .dts configuration file to make sure these resources are not in use on the Linux side.

One specific topic in this discussion is allocation of DMA controllers between the M4 and Cortex-A cores. There are separate hardware DMA controllers that can be assigned (or not) to any core as they are simply peripherals. The M4 DMA channels are connected to the AHB bus while the Cortex-A7 core(s) are connected to the Master (MDMA) via the AXI bus. These buses are connected via the Master DMA (IPCC) but the scope of the DMA channels can be configured to be dedicated.